ML Channel ASIC Chip Tape Out

Objective: Practical viability of ML data detection channel for HDDs.
Feature: ASIC implementation of a Convolution-Neural-Network ML data channel.

We have completed a ASIC design of CNN-ML data channel for a TDMR setting of two readers. It has been submitted to TSMC for IC fabrication and due back in July, 2021. The simulation shows the chip shows slightly improved performance comparing with current HDD channels and can operate at 200+ MHz data rate with latency <1 μsand similar power consumption with today’s HDD channel chip.

TDMR CNN Detector Chip Tape-out