Data Storage Systems Center

Applying low-density parity check (LDPC) codes to practical data storage systems still have some problems to overcome. Typical hard disk drive systems require bit error rates (BERs) around 10-12 to 10-15. To evaluate the performance of LDPC code at such low BERs, Monte Carlo simulation needs to process an enormous number of bits to yield only a few errors. The fastest FPGA emulation platform reported up to date, can only reach BER between 10-11 and 10-12 in magnetic recording channels. We employ a highly-parallel FPGA processing cluster to emulate the data storage system, allowing us to achieve the computational speed necessary to characterize the performance of LDPC codes near 10-14 BER. Another critical issue for real LDPC application is power consumption, as disk drive read/write systems are very cost sensitive. Power dissipation has to be low enough to allow inexpensive packaging and system cooling. We investigate the potential power-efficient techniques for LDPC decoder design in many levels, including decoding algorithms, architecture exploration, and circuit optimization.

Characterizing the error floor of low-density parity check (LDPC) codes requires the processing of an enormous number of bits to yield only a few errors. Conventional workstation-based simulation does not have sufficient computational performance to execute this characterization in a tractable amount of time. We employ a pipelined, highly-parallel FPGA emulation of a data storage system to achieve the computational speed necessary to characterize LDPC code error floors. To date, we have used pipelining and logic optimization to increase the core module clock rate by 5x over the previous FPGA emulation effort. We are pursuing further core module enhancements as well as a parallelized implementation to achieve an overall speedup of >50x over the previous FPGA effort (equivalent to >1000x over a workstation implementation).